| --- Log opened Thu Nov 01 00:00:46 2007 |
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| 02:46 | < blkr3b3l> | hello |
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| 12:16 | < MyCatSchemes> | Damn, Feynman was awesome. |
| 12:19 | < Vornicus> | Yes. |
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| 19:30 | <@ToxicFrog> | Woo, CPU design finalized! |
| 19:30 | <@ToxicFrog> | Turns out we need two clocks per instruction, though, since we aren't implementing DDR memory. |
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| 20:06 | < Vornicus> | So your code and data paths are the same? |
| 20:06 | < Vornicus> | well, when you get down to the memory, that is? |
| 20:14 | <@ToxicFrog> | Yeah. Changing that is part of phase 4, pipelining. |
| 20:14 | <@ToxicFrog> | We've been explicitly told not to do that kind of optimization yet. |
| 20:16 | <@ToxicFrog> | We were originally thinking we could do LOAD on the rising edge and EXECUTE on the falling edge, but no go. |
| 20:16 | < Vornicus> | So you do end up needing pipelining |
| 20:17 | <@ToxicFrog> | Yep. |
| 20:17 | <@ToxicFrog> | But that comes later. |
| 20:18 | <@ToxicFrog> | Phase 2 is just design of non-pipelined data and control paths. |
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| --- Log closed Fri Nov 02 00:00:52 2007 |